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s3c72n2/c72n4/p72n4 sam47 instruction set 5- 1 5 sam47 instruction s et overview the sam47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and cpu control. i/o instructions for peripheral hardware devices are flexible and easy to use. symbolic hardware names can be substituted as the instruction operand in place of the actual address. other important features of the sam47 instruction set include: ? 1-byte referencing of long instructions (ref instruction) ? redundant instruction reduction (string effect) ? skip feature for adc and sbc instructions instruction operands conform to the operand format defined for each instruction. several instructions have multiple operand formats. predefined values or labels can be used as instruction operands when addressing immediate data. many of the symbols for specific registers and flags may also be substituted as labels for operations such da, mema, memb, b, and so on. using instruction labels can greatly simplify program writing and debugging tasks. instruction set features in this chapter, the following sam47 instruction set features are described in detail: ? instruction reference area ? i nstruction redundancy reduction ? flexible bit manipulation ? adc and sbc instruction skip condition note the rom size accessed by instruction may change for s3c72n2 and S3C72N4.
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 2 instruction reference area using the 1-byte ref (reference) instruction, you can reference instructions stored in addresses 0020h?007fh of program memory (the ref instruction look-up table). the location referenced by ref may contain either two 1-byte instructions or a single 2-byte instruction. the starting address of the instruction being referenced must always be an even number. 3-byte instructions such as jp or call may also be referenced using ref. to reference these 3-byte instructions, the 2-byte pseudo commands tjp and tcall must be written in the reference. the pc is not incremented when a ref instruction is executed. after it executes, the program's instruction execution sequence resumes at the address immediately following the ref instruction. by using ref instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the program size. to summarize, the ref instruction can be used in three ways: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions; ? branching to any location by referencing a branch address that is stored in the look-up table; ? calling subroutines at any location by referencing a call address that is stored in the look-up table. if necessary, a ref instruction can be circumvented by means of a skip operation prior to the ref in the execution sequence. in addition, the instruction immediately following a ref can also be skipped by using an appropriate reference instruction or instructions. two-byte instructions can be referenced by using a ref instruction. (an exception is xch a,da * ) if the msb value of the first 1-byte instruction in the reference area is ?0?, the instruction cannot be referenced by a ref instruction. therefore, if you use ref to reference two 1-byte instructions stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. these combinations are described in table5- 1. table 5-1. valid 1-byte instruction combinations for ref look-ups first 1-byte instruction second 1-byte instruction instruction operand instruction operand ld a,#im incs* r incs rrb decs* r ld a,@rrq incs* r incs rrb decs* r ld @hl,a incs* r incs rrb decs* r note : if the msb value of the first one-byte binary code in instruction is "0", the instruction cannot be referenced by a ref instruction.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 3 reducing instruction redundancy when redundant instructions such as ld a,#im and ld ea,#imm are used consecutively in a program sequence, only the first instruction is executed. the redundant instructions which follow are ignored, that is, they are handled like a nop instruction. when ld hl,#imm instructions are used consecutively, redundant instructions are also ignored. in the following example, only the 'ld a, # im' instruction will be executed. the 8-bit load instruction which follows it is interpreted as redundant and is ignored: ld a,#im ; load 4-bit immediate data (# im) to accumulator ld ea,#imm ; load 8-bit immediate data (# imm) to extended ; accumulator in this example, the statements 'ld a,#2h' and 'ld a,#3h' are ignored: bitr emb ld a,#1h ; execute instruction ld a,#2h ; ignore, redundant instruction ld a,#3h ; ignore, redundant instruction ld 23h,a ; execute instruction, 023h ? #1h if consecutive ld hl, # imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, hl) are detected, only the first ld is executed and the lds which immediately follow are ignored. for example, ld hl,#10h ; hl ? 10h ld hl,#20h ; ignore, redundant instruction ld a,#3h ; a ? 3h ld ea,#35h ; ignore, redundant instruction ld @hl,a ; (10h) ? 3h if an instruction reference with a ref instruction has a redundancy effect, the following conditions apply: ? if the instruction preceding the ref has a redundancy effect, this effect is canceled and the referenced instruction is not skipped. ? if the instruction following the ref has a redundancy effect, the instruction following the ref is skipped. + + p rogramming tip ? example of the instruction redundancy effect org 0020h abc ld ea,#30h ; stored in ref instruction reference area org 0080h ? ? ? ld ea,#40h ; redundancy effect is encountered ref abc ; no skip (ea ? #30h) ? ? ? ref abc ; ea ? #30h ld ea,#50h ; skip
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 4 flexible bit manipulation in addition to normal bit manipulation instructions like set and clear, the sam47 instruction set can also perform bit tests, bit transfers, and bit boolean operations. bits can also be addressed and manipulated by special bit addressing modes. three types of bit addressing are supported: ? mema.b ? memb.@l ? @ h+da.b the parameters of these bit addressing modes are described in more detail in table 5-2. table 5-2. bit addressing modes and parameters addressing mode addressable peripherals address range mema.b erb, emb, is1, is0, iex, irqx fb0h?fbfh ports 1, 2, 3, 6 ff0h?fffh memb.@l ports 1, 2, 3, 6, and bsc fc0h?fffh @ h+da.b all bit- manipulable peripheral hardware all bits of the memory bank specified by emb and smb that are bit- manipulable instructions which have skip conditions the following instructions have a skip function when an overflow or borrow occurs: xchi incs xchd decs ldi ads ldd sbs if there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. however, the carry flag value is unaffected. the instructions btst, btsf, and cpse also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. instructions which affect the carry flag the only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: adc ldb c,(operand) sbc band c,(operand) scf bor c,(operand) rcf bxor c,(operand) ccf
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 5 adc and sbc instruction skip conditions the instructions 'adc a,@hl' and 'sbc a,@hl' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ads a,#im'. if an 'ads a,#im' instruction immediately follows an 'adc a,@hl' or 'sbc a,@hl' instruction in a program sequence, the ads instruction does not skip the instruction following ads, even if it has a skip function. if, however, an 'adc a,@hl' or 'sbc a,@hl' instruction is immediately followed by an 'ads a,#im' instruction, the adc (or sbc) skips on overflow (or if there is no borrow) to the instruction immediately following the ads, and program execution continues. table 5-3 contains additional information and examples of the 'adc a,@hl' and 'sbc a,@hl' skip feature. table 5-3. skip conditions for adc and sbc instructions sample instruction sequences if the result of instruction 1 is: then, the execution sequence is: reason adc a,@hl ads a,#im xxx xxx 1 2 3 4 overflow no overflow 1, 3, 4 1, 2, 3, 4 ads cannot skip instruction 3, even if it has a skip function. sbc a,@hl ads a,#im xxx xxx 1 2 3 4 borrow no borrow 1, 2, 3, 4 1, 3, 4 ads cannot skip instruction 3, even if it has a skip function.
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 6 symbols and conventions table 5-4. data type symbols symbol data type d immediate data a address data b bit data r register data f flag data i indirect addressing data t memc 0.5 immediate data table 5-5. register identifiers full register name id 4-bit accumulator a 4-bit working registers e, l, h, x, w, z, y 8-bit extended accumulator ea 8-bit memory pointer hl 8-bit working registers wx, yz, wl select register bank 'n' srb n select memory bank 'n' smb n carry flag c program status word psw port 'n' pn 'm'- th bit of port 'n' pn.m interrupt priority register ipr enable memory bank flag emb enable register bank flag erb table 5-6. instruction operand notation symbol definition da direct address @ indirect address prefix src source operand dst destination operand (r) contents of register r .b bit location im 4-bit immediate data (number) imm 8-bit immediate data (number) # immediate data prefix adr 000h?1fffh immediate address adrn 'n' bit address r a, e, l, h, x, w, z, y ra e, l, h, x, w, z, y rr ea, hl, wx, yz rra hl, wx, wl rrb hl, wx, yz rrc wx, wl mema fb0h?fbfh, ff0h?fffh memb fc0h?fffh memc code direct addressing: 0020h?007fh sb select bank register (8 bits) xor logical exclusive-or or logical or and logical and [(rr)] contents addressed by rr
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 7 opcode definitions table 5-7. opcode definitions (direct) register r2 r1 r0 a 0 0 0 e 0 0 1 l 0 1 0 h 0 1 1 x 1 0 0 w 1 0 1 z 1 1 0 y 1 1 1 ea 0 0 0 hl 0 1 0 wx 1 0 0 yz 1 1 0 r = immediate data for register table 5-8. opcode definitions (indirect) register i2 i1 i0 @hl 1 0 1 @wx 1 1 0 @wl 1 1 1 i = immediate data for indirect addressing calculating additional machine cycles for skips a machine cycle is defined as one cycle of the selected cpu clock. three different clock rates can be selected using the pcon register. in this document, the letter 's' is used in tables when describing the number of additional machine cycles re quired for an instruction to execute, given that the instruction has a skip function ('s' = skip). the addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped ? whether it is a 1-byte, 2-byte, or 3-byte instruction. a skip is also executed for smb and srb instructions. the values in additional machine cycles for 's' for the three cases in which skip conditions occur are as follows: case 1: no skip s = 0 cycles case 2: skip is 1-byte or 2-byte instruction s = 1 cycle case 3: skip is 3-byte instruction s = 2 cycles note : ref instructions are skipped in one machine cycle.
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 8 high-level summary this chapter contains a high-level summary of the sam47 instruction set in table format. the tables are designed to familiarize you with the range of instructions that are available in each instruction category. these tables are a useful quick-reference resource when writing application programs. if you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. the following information is provided for each instruction: ? instruction name ? operand(s) ? brief operation description ? number of bytes of the instruction and op erand(s) ? number of machine cycles required to execute the instruction the tables in this chapter are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 9 table 5-9. cpu control instructions ? high-level summary name operand operation description bytes cycles scf set carry flag to logic one 1 1 rcf reset carry flag to logic zero 1 1 ccf complement carry flag 1 1 ei enable all interrupts 2 2 di disable all interrupts 2 2 idle engage cpu idle mode 2 2 stop engage cpu stop mode 2 2 nop no operation 1 1 smb n select memory bank 2 2 srb n select register bank 2 2 ref memc reference code 1 3 ventn emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location 2 2 table 5-10. program control instructions ? high-level summary name operand operation description bytes cycles cpse r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s jp adr12 jump to direct address (12 bits) 3 3 jps adr12 jump direct in page (12 bits) 2 2 jr # im jump to immediate address 1 2 @wx branch relative to wx register 2 3 @ea branch relative to ea 2 3 call adr12 call direct address (12 bits) 3 4 calls adr11 call direct address within 2 k (11 bits) 2 3 ret ? return from subroutine 1 3 iret ? return from interrupt 1 3 sret ? return from subroutine and skip 1 3 + s
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 10 table 5-11. data transfer instructions ? high-level summary name operand operation description bytes cycles xch a,da exchange a and direct data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory con tents 2 2 xchi a,@hl exchange a and indirect data memory contents; increment contents of register l and skip on carry 1 2 + s xchd a,@hl exchange a and indirect data memory contents; decrement contents of register l and skip on carry 1 2 + s ld a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 ldi a,@hl load indirect data memory to a; increment register l contents and skip on carry 1 2 + s ldd a,@hl load indirect data memory contents to a; decrement register l contents and skip on carry 1 2 + s ldc ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 rrc a rotate right through carry bit 1 1 push rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 pop rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 11 table 5-12. logic instructions ? high-level summary name operand operation description bytes cycles and a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 or a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 xor a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 com a complement accumulator (a) 2 2 table 5-13. arithmetic instructions ? high-level summary name operand operation description bytes cycles adc a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 ads a, # im add 4-bit immediate data to a and skip on carry 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on carry 2 2 + s a,@hl add indirect data memory to a and skip on carry 1 1 + s ea,rr add register pair (rr) contents to ea and skip on carry 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on carry 2 2 + s sbc a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 sbs a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s decs r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s incs r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 12 rrb increment register pair ( rrb); skip on carry 1 1 + s
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 13 table 5-14. bit manipulation instructions ? high-level summary name operand operation description bytes cycles btst c test specified bit and skip if carry flag is set 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b memb.@l @ h+da.b btsf da.b test specified memory bit and skip if bit equals "0" mema.b memb.@l @ h+da.b btstz mema.b test specified bit; skip and clear if memory bit is set memb.@l @ h+da.b bits da.b set specified memory bit 2 2 mema.b memb.@l @ h+da.b bitr da.b clear specified memory bit to logic zero mema.b memb.@l @ h+da.b band c,mema.b logical-and carry flag with specified memory bit c,memb.@l c,@h+da.b bor c,mema.b logical-or carry with specified memory bit c,memb.@l c,@h+da.b bxor c,mema.b exclusive-or carry with specified memory bit c,memb.@l c,@h+da.b ldb mema.b,c load carry bit to a specified memory bit memb.@l,c load carry bit to a specified indirect memory bit @ h+da.b,c c,mema.b load specified memory bit to carry bit c,memb.@l load specified indirect memory bit to carry bit c,@h+da.b
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 14 binary code summary this chapter contains binary code values and operation notation for each instruction in the sam47 instruction set in an easy-to-read, tabular format. it is intended to be used as a quick-reference source for programmers who are experienced with the sam47 instruction set. the same binary values and notation are also included in the detailed descriptions of individual instructions later in chapter 5. if you are reading this user's manual for the first time, please just scan this very detailed information briefly. most of the general information you will need to write application programs can be found in the high-level sum mary tables in the previous chapter. the following information is provided for each instruction: ? instruction name ? operand(s) ? binary values ? operation notation the tables in this chapter are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 15 table 5-15. cpu control instructions ? binary code summary name operand binary code operation notation scf 1 1 1 0 0 1 1 1 c ? 1 rcf 1 1 1 0 0 1 1 0 c ? 0 ccf 1 1 0 1 0 1 1 0 c ? c ei 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 di 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 idle 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 stop 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 nop 1 0 1 0 0 0 0 0 no operation smb n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 srb n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 ref memc t7 t6 t5 t4 t3 t2 t1 t0 pc11?0 = memc7?4, memc3?0 <1 ventn emb (0,1) erb (0,1) adr e m b e r b 0 0 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0 rom (2 x n) 3?0 ? pc11?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 16 table 5-16. program control instructions ? binary code summary name operand binary code operation notation cpse r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 jp adr12 1 1 0 1 1 0 1 1 pc11?0 ? adr12 0 0 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 jps adr12 1 0 0 1 a11 a10 a9 a8 pc11?0 ? adr12 a7 a6 a5 a4 a3 a2 a1 a0 jr # im * pc11?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc11?0 ? pc11?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc11?0 ? pc11?8 + (ea) 0 1 1 0 0 0 0 0 call adr12 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb [(sp?3) (sp?4)] ? pc7?0 0 1 0 0 a11 a10 a9 a8 [(sp?5) (sp?6)] ? pc11?8 sp ? sp - 6 a7 a6 a5 a4 a3 a2 a1 a0 pc11?0 ? adr12 calls adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc11?8 a7 a6 a5 a4 a3 a2 a1 a0 sp ? sp - 6 pc11 ? 0 pc10?0 ? adr11 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 17
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 18 table 5-16. program control instructions ? binary code summary (continued) name operand binary code operation notation ret ? 1 1 0 0 0 1 0 1 pc11?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 iret ? 1 1 0 1 0 1 0 1 pc11?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 sret ? 1 1 1 0 0 1 0 1 pc11?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6, then skip table 5-17. data transfer instructions ? binary code summary name operand binary code operation notation xch a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 xchi a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h xchd a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh ld a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 19 table 5-17. data transfer instructions ? binary code summary (continued) name operand binary code operation notation ld ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0 rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 ldi a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h ldd a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh ldc ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc11?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc11?8 + (ea)] rrc a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) push rr 0 0 1 0 1 r2 r1 1 ((sp?1)) ((sp?2)) ? (rr), (sp) ? (sp)?2 sb 1 1 0 1 1 1 0 1 ((sp?1)) ? (smb), ((sp?2)) ? (srb), (sp) ? (sp)?2 0 1 1 0 0 1 1 1
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 20 table 5-17. data transfer instructions ? binary code summary (concluded) name operand binary code operation notation pop rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp + 1) sp ? sp + 2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp + 1), sp ? sp + 2 0 1 1 0 0 1 1 0 table 5-18. logic instructions ? binary code summary name operand binary code operation notation and a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 or a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 xor a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 com a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 21 table 5-19. arithmetic instructions ? binary code summary name operand binary code operation notation adc a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 ads a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on carry ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on carry d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a+ (hl); skip on carry ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on carry 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on carry 1 0 0 1 0 r2 r1 0 sbc a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 sbs a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 decs r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 incs r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 22 table 5-20. bit manipulation instructions ? binary code summary name operand binary code operation notation btst c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 btsf da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3?2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @h da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 btstz mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 bits da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 23 table 5-20. bit manipulation instructions ? binary code summary (continued) name operand binary code operation notation bitr da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 band c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bor c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bxor c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h
sam47 instruction set s3c72n2 /c72n4/p72n4 5- 24 table 5-20. bit manipulation instructions ? binary code summary (concluded) name operand binary code operation notation ldb mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b * 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 25 instruction descriptions this chapter contains detailed information and programming examples for each instruction of the sam47 instruction set. information is arranged in a consistent format to improve readability and for use as a quick-reference re source for application programmers. if you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. the information elements of the instruction description format are as follows: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? operation overview (from the "high-level summary" table) ? textual description of the instruction's effect ? binary code overview (from the "binary code summary" table) ? programming example(s) to show how the instruction is used
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 26 adc ? add with carry adc dst,src operation: operand operation summary bytes cycles a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 description: the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. if 'adc a,@hl' is followed by an 'ads a,#im' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. (this condition is valid only for 'adc a,@hl' instructions. if an overflow occurs following an 'ads a,#im' instruction, the next instruction will not be skipped.) operand binary code operation notation a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" adc ea,hl ; ea ? 0c3h + 0aah + 1h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" adc ea,hl ; ea ? 0c3h + 0aah + 0h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 27 adc ? add with carry adc (continued) examples: 3. if adc a,@hl is followed by an ads a,#im, the adc skips on carry to the instruction immediately after the ads. an ads instruct ion immediately after the adc does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 28 ads ? add and skip on overflow ads dst,src operation: operand operation summary bytes cycles a, # im add 4-bit immediate data to a and skip on overflow 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on overflow 2 2 + s a,@hl add indirect data memory to a and skip on overflow 1 1 + s ea,rr add register pair (rr) contents to ea and skip on overflow 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on overflow 2 2 + s description: the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. if 'ads a,#im' follows an 'adc a,@hl' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. this skip condition is valid only for 'adc a,@hl' instructions, however. if an overflow occurs following an ads instruction, the next instruction is not skipped. operand binary code operation notation a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on overflow ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on overflow d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a + (hl); skip on overflow ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on overflow 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on overflow 1 0 0 1 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 0aah = 6dh, c ? "0" ; ads skips on overflow, but carry flag value is not a ffected. jps xxx ; this instruction is skipped since ads had an overflow. jps yyy ; jump to yyy.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 29 ads ? add and skip on overflow ads (continued) examples: 2. if the extended accumulator contains the value 0c3h, register pair hl the value 12h, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 12h = 0d5h, c ? "0" jps xxx ; jump to xxx; no skip after ads. 3. if 'adc a,@hl' is followed by an 'ads a,#im', the adc skips on overflow to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'adc a,@hl' does not skip even if overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result. jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 30 and ? logical and and dst,src operation: operand operation summary bytes cycles a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 description: the source operand is logically anded with the destination operand. the result is stored in the destination. the logical and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both "1"; otherwise a "0" bit is stored. the contents of the source are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 example: if the extended accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction and ea,hl leaves the value 41h (01000001b) in the extended accumulator ea .
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 31 band ? bit logical and band c,src.b operation: operand operation summary bytes cycles c,mema.b logical-and carry flag with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically anded with the carry flag bit value. if the boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. the bit value of the source operand is not affected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the following instructions set the carry flag if p1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): smb 15 ; c ? "1" band c,p1.0 ; if p1.0 = "1", c ? "1" ; if p1.0 = "0", c ? "0" 2. assume the p1 address is ff1h and the value for register l is 9h (1001b). the address (memb.7?2) is 111100b; (l.3?2) is 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the band instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h band c,p1.@l ; p1.@l is specified as p2.1 ; c and p2.1
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 32 band ? bit logical and band (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag (3?0) is 0000b. the resulting addre ss is 00100000b or 20h. the bit value for the band instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h band c,@h+flag ; c and flag (20h.3)
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 33 bitr ? bit reset bitr dst.b operation: operand operation summary bytes cycles da.b clear specified memory bit to logic zero 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: a bitr instruction clears to logic zero (resets) the specified bit within the destination operand. no other bits in the destination are affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. bit location 30h.2 in the ram has a current value of logic one. the followin g instruction clears the third bit in ram location 30h (bit 2) to logic zero: bitr 30h.2 ; 30h.2 ? "0" 2. you can use bitr in the same way to manipulate a port address bit: bitr p2.0 ; p2.0 ? "0"
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 34 bitr ? bit reset bitr (continued) examples: 3. assuming that p2.2, p2.3, and p3.0?p3.3 are cleared to "0": ld l,#0ah bp2 bitr p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 incs l jr bp2 4. if bank 0, location 0a0h.0 is cleared (and regardless of whether the emb value is logic zero), bitr has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bitr @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "0? note: since the bitr instruction is used for output functions, the pin names used in the examples above may change for different devices in the sam47 product family.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 35 bits ? bit set bits dst.b operation: operand operation summary bytes cycles da.b set specified memory bit 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: this instruction sets the specified bit within the destination without affecting any other bits in the destination. bits can manipulate any bit that is addressable using direct or indirect addressing modes. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. assuming that bit location 30h.2 in the ram has a current value of "0", the following instruction sets the second bit of location 30h to "1". bits 30h.2 ; 30h.2 ? "1" 2. you can use bits in the same way to manipulate a port address bit: bits p2.0d ; p2.0 ? "1"
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 36 bits ? bit set bits (continued) examples: 3. given that p2.2, p2.3, and p3.0?p3.3 are set to "1": ld l,#0ah bp2 bits p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 incs l jr bp2 4. if bank 0, location 0a0h.0, is set to "1" and the emb = "0", bits has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bits @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "1" note: since the bits instruction is used for output functions, pin names used in the examples above may change for different devices in the sam47 product family.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 37 bor ? bit logical or bor c,src.b operation: operand operation summary bytes cycles c,mema.b logical-or carry with specified memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically ored with the carry flag bit value. the value of the source is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the carry flag is logically ored with the p1.0 value: rcf ; c ? "0" bor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the address (memb.7? 2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bor instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h bor c,p1.@l ; p1.@l is specified as p2.1; c or p2.1
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 38 bor ? bit logical or bor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bor c,@h+flag ; c or flag (20h.3)
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 39 btsf ? bit test and skip on false btsf dst.b operation: operand operation summary bytes cycles da.b test specified memory bit and skip if bit equals "0" 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "0", the btsf instruction skips the instruction which immediately follows it; otherwise the instruction following the btsf is executed. the destination bit value is not affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3-2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @h + da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will ca use the program to continue execution from the instruction identified as label2: btsf 30h.2 ; if 30h.2 = "0", then skip ret ; if 30h.2 = "1", return jp label2 2. you can use btsf in the same way to manipulate a port pin address bit: btsf p2.0 ; if p2.0 = "0", then skip ret ; if p2.0 = "1", then return jp label3
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 40 btsf ? bit test and skip on false btsf (continued) examples: 3. p2.2, p2.3 and p3.0?p3.3 are tested: ld l,#0ah bp2 btsf p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btsf has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btsf @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "0", then skip ret ? ? ?
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 41 btst ? bit test and skip on true btst dst.b operation: operand operation summary bytes cycles c test carry bit and skip if set (= "1") 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is "1", the instruction that immediately follows the btst instruction is skipped; otherwise the instruction following the btst instruction is executed. the destination bit value is not affected. operand binary code operation notation c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will execute the ret instruction: btst 30h.2 ; if 30h.2 = "1", then skip ret ; if 30h.2 = "0", return jp la bel2
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 42 btst ? bit test and skip on true btst (continued) examples: 2. you can use btst in the same way to manipulate a port pin address bit: btst p2.0 ; if p2.0 = "1", then skip ret ; if p2.0 = "0", then return jp label3 3. assume that p2.2, p2.3 and p3.0?p3.3 are cleared to "0": ld l,#0ah bp2 btst p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btst has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btst @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", then skip ret ? ? ?
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 43 btstz ? bit test and skip on true; clear bit btstz dst.b operation: operand operation summary bytes cycles mema.b test specified bit; skip and clear if memory bit is set 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "1", the instruction immediately following the btstz instruction is skipped; otherwise the instruction following the btstz is executed. the destination bit value is cleared. operand binary code operation notation mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. port pin p2.0 is toggled by checking the p2.0 value (level): btstz p2.0 ; if p2.0 = "1", then p2.0 ? "0" and skip bits p2.0 ; if p2.0 = "0", then p2.0 ? "1" jp label3 2. assume that port pins p2.2, p2.3 and p3.0?p3.3 are toggled: ld l,#0ah bp2 btstz p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 44 btstz ? bit test and skip on true; clear bit btstz (continued) examples: 3. bank 0, location 0a0h.0, is tested and emb = "0" : flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btstz @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", clear and skip bits @h+flag ; if 0a0h.0 = "0", then 0a0h.0 ? "1"
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 45 bxor ? bit exclusive or bxor c,src.b operation: operand operation summary bytes cycles c,mema.b exclusive-or carry with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically xored with the carry bit value. the resultant bit is written to the carry flag. the source value is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3-2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the carry flag is logically xored with the p1.0 value: rcf ; c ? "0" bxor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bxor instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h bxor c,p1.@l ; p1.@l is specified as p2.1; c xor p2.1
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 46 bxor ? bit exclusive or bxor (continued) examples: 3. register h contains the v alue 2h and flag = 20h.3. the address of h is 0010b and flag(3?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bxor c,@h+flag ; c xor flag (20h.3)
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 47 call ? call procedure call dst operation: operand operation summary bytes cycles adr12 call direct address(12 bits) 3 4 description: call calls a subroutine located at the destination address. the instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. the emb and erb are also pushed to the stack. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the full 14-kbyte program memory address space. operand binary code operation notation adr12 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb [(sp?3) (sp?4)] ? pc7?0 0 1 0 a12 a11 a10 a9 a8 [(sp?5) (sp?6)] ? pc11?8 sp ? sp - 6 a7 a6 a5 a4 a3 a2 a1 a0 pc11?0 ? adr12 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0e3fh. executing the instruction call play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 6h 0fbh = 0h 0fah = 1h pc = 0e3fh data is written to stack locations 0ffh?0fah as follows: 0fah pc11 ? pc8 0fbh 0 0 0 0 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 48 calls ? call procedure (short) calls dst operation: operand operation summary bytes cycles adr11 call direct address within 2 k (11 bits) 2 3 description: the calls instruction unconditionally calls a subroutine located at the indicated address. the instruction increments the pc twice to obtain the address of the following instruction. then, it pushes the result onto the stack, decreasing the stack pointer six times. the higher bits of the pc, with the exception of the lower 11 bits, are cleared. the subroutine call must therefore be located within the 2-kbyte block (0000h?07ffh) of program memory. operand binary code operation notation adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc11?8 a7 a6 a5 a4 a3 a2 a1 a0 sp ? sp - 6 pc11 ? 0 pc10?0 ? adr11 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0345h. executing the instruction calls play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 5h 0fbh = 0h 0fah = 1h pc = 0345h data is written to stack locations 0ffh?0fah as follows: 0fah pc11 ? pc8 0fbh 0 0 0 0 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 49 ccf ? complement carry flag ccf operation: operand operation summary bytes cycles ? complement carry flag 1 1 description: the carry flag is complemented; if c = "1" it is changed to c = "0" and vice-versa. operand binary code operation notation ? 1 1 0 1 0 1 1 0 c ? c example: if the carry flag is logic zero, the instruction ccf changes the value to logic one.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 50 com ? complement accumulator com a operation: operand operation summary bytes cycles a complement accumulator (a) 2 2 description: the accumulator value is complemented; if the bit value of a is "1", it is changed to "0" and vice versa. operand binary code operation notation a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1 example: if the accumulator contains the value 4h (0100b), the instruction com a leaves the value 0bh (1011b) in the accumulator.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 51 cpse ? compare and skip if equal cpse dst,src operation: operand operation summary bytes cycles r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s description: cpse compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. neither operand is affected by the comparison. operand binary code operation notation r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 example: the extended accumulator contains the value 34h and register pair hl contains 56h. the second instruction (ret) in the instruction sequence cpse ea,hl ret is not skipped. that is, the subroutine returns since the result of the comparison is 'not equal.'
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 52 decs ? decrement and skip on borrow decs dst operation: operand operation summary bytes cycles r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s description: the destination is decremented by one. an original value of 00h will underflow to 0ffh. if a borrow occurs, a skip is executed. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 examples: 1. register pair hl contains the value 7fh (01111111b). the following instruction leaves the value 7eh in register pair hl: decs hl 2. register a contains the value 0h. the following instruction sequence leaves the value 0ffh in register a. since a "borrow" occurs, the 'call play1' instruction is skipped and the 'call play2' instruction is executed: decs a ; "borrow" occurs call play1 ; skipped call play2 ; executed
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 53 di ? disable interrupts di operation: operand operation summary bytes cycles ? disable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr, ime, is cleared to logic zero, disabling all interrupts. interrupts can still set their respective interrupt status latches, but the cpu will not directly service them. operand binary code operation notation ? 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic one (e.g., all instructions are enabled), the instruction di sets the ime bit to logic zero, disabling all interrupts.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 54 ei ? enable interrupts ei operation: operand operation summary bytes cycles ? enable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr (ime) is set to logic one. this allows all interrupts to be serviced when they occur, assuming they are enabled. if an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. operand binary code operation notation ? 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic zero (e.g., all instructions are disabled), the instruction ei sets the ime bit to logic one, enabling all interrupts.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 55 idle ? idle operation idle operation: operand operation summary bytes cycles ? engage cpu idle mode 2 2 description: idle causes the cpu clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (pcon). after an idle instruction has been executed, peripheral hardware remains operative. in application programs, an idle instruction mus t be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three nop instructions are not used after idle instruction, leakage current could be flown because of the floating state in the internal bus. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 example: the instruction sequence idle nop nop nop sets bit 2 of the pcon register to logic one, stopping the cpu clock. the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 56 incs ? increment and skip on carry incs dst operation: operand operation summary bytes cycles r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair ( rrb); skip on carry 1 1 + s description: the instruction incs increments the value of the destination operand by one. an original value of 0fh will, for example, overflow to 00h. if a carry occurs, the next instruction is skipped. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry example: register pair hl contains the value 7eh (01111110b). ram location 7eh contains 0fh. the instruction sequence incs @hl ; 7eh ? "0" incs hl ; skip incs @hl ; 7eh ? "1" leaves the register pair hl with the value 7eh and ram location 7eh with the value 1h. since a carry occurred, the second instruction is skipped. the carry flag value remains unchanged.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 57 iret ? return from interrupt iret operation: operand operation summary bytes cycles ? return from interrupt 1 3 description: iret is used at the end of an interrupt service routine. it pops the pc values successively from the stack and restores them to the program counter. the stack pointer is incremented by six and the psw, enable memory bank (emb) bit, and enable register bank (erb) bit are also automatically restored to their pre-interrupt values. program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower-level or same-level interrupt was pending when the iret was executed, iret will be executed before the pending interrupt is processed. operand binary code operation notation ? 1 1 0 1 0 1 0 1 pc11?8 ? (sp + 1) (sp) pc7?0 ? sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 example: the stack pointer contains the value 0fah. an interrupt is detected in the instruction at location 0122h. ram locations 0fdh, 0fch, and 0fah contain the values 2h, 3h, and 1h, respectively. the instruction iret leaves the stack pointer with the value 00h and the program returns to continue execution at location 123h. during a return from interrupt, data is popped from the stack to the program counter. the data in stack locations 0ffh?0fah is organized as follows: 0fah pc11 ? pc8 0fbh 0 0 0 0 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh is1 is0 emb erb 0ffh c sc2 sc1 sc0
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 58 jp ? jump jp dst operation: operand operation summary bytes cycles adr12 jump to direct address (12 bits) 3 3 description: jp causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. the destination can be anywhere in the 4-kbyte program memory address space. operand binary code operation notation adr12 1 1 0 1 1 0 1 1 pc11?0 ? adr12 0 0 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'syscon' is assigned to the instruction at program location 07ffh. the instruction jp syscon at location 0123h will load the program counter with the value 07ffh.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 59 jps ? jump (short) jps dst operation: operand operation summary bytes cycles adr12 jump direct in page (12 bits) 2 2 description: jps causes an unconditional branch to the indicated address with the 4-kbyte program memory address space. bits 0?11 of the program counter are replaced with the directly specified address. the destination address for this jump is specified to the assembler by a label or by an actual address in program memory. operand binary code operation notation adr12 1 0 0 1 a11 a10 a9 a8 pc11?0 ? adr12 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'sub' is assigned to the instruction at program memory location 00ffh. the instruction jps sub at location 0eabh will load the program counter with the value 00ffh.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 60 jr ? jump relative (very short) jr dst operation: operand operation summary bytes cycles # im branch to relative immediate address 1 2 @wx branch relative to contents of wx register 2 3 @ea branch relative to contents of ea 2 3 description: jr causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the pc. the range of the relative address is current pc ? 15 to current pc + 16. the destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (?). for immediate addressing, the (+) range is from 2 to 16 and the (?) range is from ?1 to ?15. if a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. for jr @wx and jr @ea branch relative instructions, the valid range for the relative address is 0h? 0ffh. the destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. normally, the 'jr @wx' and 'jr @ea' instructions jump to the address in the page in which the instruction is located. however, if the first byte of the instruction code is located at address 0xfeh or 0xffh, the instruction will jump to the next page. operand binary code operation notation # im * pc11?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc11?0 ? pc11?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc11?0 ? pc11?8 + (ea) 0 1 1 0 0 0 0 0 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 61 jr ? jump relative (very short) jr (continued) examples: 1. a short form for a relative jump to label 'kk' is the instruction jr kk where 'kk' must be within the allowed range of current pc?15 to current pc+16. the jr instruction has in this case the effect of an unconditional jp instruction. 2. in the following instruction sequence, if the instruction 'ld wx, #02h' were to be executed in place of 'ld wx,#00h', the program would jump to 0502h and ' jps bbb' would be executed. if 'ld ea,#04h' were to be executed, the jump would be to 0504h and ' jps ccc' would be executed. org 0500h jps aaa jps bbb jps ccc jps ddd ld wx,#00h ; wx ? 00h ld ea,wx ads wx,ea ; wx ? (wx) + (wx) jr @wx ; current pc11?8 (05h) + wx (00h) = 0500h ; jump to address 0500h and execute jps aaa 3. here is another example: org 0600h ld a,#0h ld a,#1h ld a,#2h ld a,#3h ld 30h,a ; address 30h ? a jps yyy xxx ld ea,#00h ; ea ? 00h jr @ea ; jump to address 0600h ; address 30h ? 0h if 'ld ea,#01h' were to be executed in place of 'ld ea,#00h', the program would jump to 0601h and address 30h would contain the value 1h. if 'ld ea,#02h' were to be executed, the jump would be to 0602h and address 30h would contain the value 2h.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 62 ld ? load ld dst,src operation: operand operation summary bytes cycles a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 description: the contents of the source are loaded into the destination. the source's contents are unaffected. if an instruction such as 'ld a,#im' (ld ea,#imm) or 'ld hl,#imm' is written more than two times in succession, only the first ld will be executed; the other similar instructions that immediately follow the first ld will be treated like a nop. this is called the 'redundancy effect' (see examples below). operand binary code operation notation a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0 ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 63 ld ? load ld (continued) description: operand binary code operation notation rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 examples: 1. ram location 30h contains the value 4h. the ram location values are 40h, 41h, and 0ah, 3h respectively. the following instruction sequence leaves the value 40h in point pair hl, 0ah in the accumulator and in ram location 40h, and 3h in register e. ld hl,#30h ; hl ? 30h ld a,@hl ; a ? 4h ld hl,#40h ; hl ? 40h ld ea,@hl ; a ? 0ah, e ? 3h ld @hl,a ; ram (40h) ? 0ah
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 64 ld ? load ld (continued) examples: 2. if an instruction such as ld a,#im (ld ea,#imm) or ld hl,#imm is written more than two times in succession, only the first ld is executed; the next instructions are treated as nops. here are two examples of this 'redundancy effect': ld a,#1h ; a ? 1h ld ea,#2h ; nop ld a,# 3h ; nop ld 23h,a ; (23h) ? 1h ld hl,#10h ; hl ? 10h ld hl,#20h ; nop ld a,#3h ; a ? 3h ld ea,#35 ; nop ld @hl,a ; (10h) ? 3h the following table contains descriptions of special characteristics of the ld instruction when used in different addressing modes: instruction operation description and guidelines ld a,#im since the 'redundancy effect' occurs with instructions like ld ea,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like nops. ld a,@rra load the data memory contents pointed to by 8-bit rra register pairs (hl, wx, wl) to the a register. ld a,da load direct data memory contents to the a register. ld a,ra load 4-bit register ra (e, l, h, x, w, z, y) to the a register. ld ra,#im load 4-bit immediate data into the ra register (e, l, h, x, w, y, z). ld rr,#imm load 8-bit immediate data into the ra register (ea, hl, wx, yz). there is a redundancy effect if the operation addresses the hl or ea registers. ld da,a load contents of register a to direct data memory address. ld ra,a load contents of register a to 4-bit ra register (e, l, h, x, w, z, y).
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 65 ld ? load ld (concluded) examples: instruction operation description and guidelines ld ea,@hl load data memory contents pointed to by 8-bit register hl to the a register, and the contents of hl+1 to the e register. the contents of register l must be an even number. if the number is odd, the lsb of register l is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to hl and the next instruction 'ld ea,@hl' loads the contents of 36h to register a and the contents of 37h to register e. ld ea,da load direct data memory contents of da to the a register, and the next direct data memory contents of da + 1 to the e register. the da value must be an even number. if it is an odd number, the lsb of da is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld ea,37h' loads the contents of 36h to the a register and the contents of 37h to the e register. ld ea,rrb load 8-bit rrb register (hl, wx, yz) to the ea register. h, w, and y register values are loaded into the e register, and the l, x, and z values into the a register. ld @hl,a load a register contents to data memory location pointed to by the 8-bit hl register value. ld da,ea load the a register contents to direct data memory and the e register contents to the next direct data memory location. the da value must be an even number. if it is an odd number, the lsb of the da value is recognized as logic zero (an even number), and is not replaced with the true value. ld rrb,ea load contents of ea to the 8-bit rrb register (hl, wx, yz). the e register is loaded into the h, w, and y register and the a register into the l, x, and z register. ld @hl,ea load the a register to data memory location pointed to by the 8-bit hl register, and the e register contents to the next location, hl + 1. the contents of the l register must be an even number. if the number is odd, the lsb of the l register is recognized as logic zero (an even number), and is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to register hl; the instruction 'ld @hl,ea' loads the contents of a into address 36h and the contents of e into address 37h.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 66 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: operand operation summary bytes cycles mema.b,c load carry bit to a specified memory bit 2 2 memb.@l,c load carry bit to a specified indirect memory bit 2 2 @ h+da.b,c 2 2 c,mema.b load memory bit to a specified carry bit 2 2 c,memb.@l load indirect memory bit to a specified carry bit 2 2 c,@h+da.b 2 2 description: the boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. one of the operands must be the carry flag; the other may be any directly or indirectly addressable bit. the source is unaffected. operand binary code operation notation mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b* 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 67 ldb ? load bit ldb (continued) examples: 1. the carry flag is set and the data value at input pin p1.0 is logic zero. the following instruction clears the carry flag to logic zero. ldb c,p1.0 2. the p1 address is ff1h and the l register contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) is 10b. the resulting address is 11110010b or ff2h and p2 is addressed. the bit value (l.1?0 ) is specified as 01b (bit 1). ld l,#9h ldb c,p1.@l ; p1.@l specifies p2.1 and c ? p2.1 3. the h register contains the value 2h and flag = 20h.3. the address for h is 0010b and for flag(3?0) the address is 0000b. the resulting address is 00100000b or 20h. the bit value is 3. therefore, @h+flag = 20h.3. flag equ 20h.3 ld h,#2h ldb c,@h+flag ; c ? flag (20h.3) 4. the following instruction sequence sets the carry flag and the loads the "1" data value to the output pin p2.0, setting it to output m ode: scf ; c ? "1" ldb p2.0,c ; p2.0 ? "1" 5. the p1 address is ff1h and l = 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) is 10b. the resulting address, 11110010b specifies p2. the bit value (l.1?0) is specified as 01b (bit 1). therefore, p1.@l = p2.1. scf ; c ? "1" ld l,#9h ldb p1.@l,c ; p1.@l specifies p2.1 ; p2.1 ? "1" 6. in this example, h = 2h and flag = 20h.3 and the address 20h is specified. since the bit value is 3, @h+flag = 20h.3: flag equ 20h.3 rcf ; c ? "0" ld h,#2h ldb @h+flag,c ; flag(20h.3) ? "0" note : port pin names used in examples 4 and 5 may vary with different sam47 devices.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 68 ldc ? load code byte ldc dst,src operation: operand operation summary bytes cycles ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 description: this instruction is used to load a byte from program memory into an extended accumulator. the address of the byte fetched is the five highest bit values in the program counter and the contents of an 8-bit working register (either wx or ea). the contents of the source are unaffected. operand binary code operation notation ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc11?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc11?8 + (ea)] examples: 1. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: ld ea,#00h call display jps main org 0500h db 66h db 77h db 88h db 99h ? ? ? display ldc ea,@ea ; ea ? address 0500h = 66h ret if the instruction 'ld ea,#01h' is executed in place of 'ld ea,#00h', the content of 0501h (77h) is loaded to the ea register. if 'ld ea,#02h' is executed, the content of address 0502h (88h) is loaded to ea.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 69 ldc ? load code byte ldc (continued) examples: 2. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: org 0500 db 66h db 77h db 88h db 99h ? ? ? display ld wx,#00h ldc ea,@wx ; ea ? address 0500h = 66h ret if the instruction 'ld wx,#01h' is executed in place of 'ld wx,#00h', then ea ? address 0501h = 77h. if the instruction 'ld wx,#02h' is executed in place of 'ld wx,#00h', then ea ? address 0502h = 88h. 3. normally, the ldc ea, @ea and the ldc ea, @wx instructions reference the table data on the page on which the instruction is located. if, however, the instruction is located at address xxffh, it will reference table data on the next page. in this example, the upper 4 bits of the address at location 0200h is loaded into register e and the lower 4 bits into register a: org 01fdh 01fdh ld wx,#00h 01ffh ldc ea,@wx ; e ? upper 4 bits of 0200h address ; a ? lower 4 bits of 0200h address 4. here is another example of page referencing with the ldc instruction: org 0100 db 67h smb 0 ld hl,#30h ; even number ld wx,#00h ldc ea,@wx ; e ? upper 4 bits of 0100h address ; a ? lower 4 bits of 0100h address ld @hl,ea ; ram (30h) ? 7, ram (31h) ? 6
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 70 ldd ? load data memory and decrement ldd dst operation: operand operation summary bytes cycles a,@hl load indirect data memory contents to a; decrement register l contents and skip on borrow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are decreased by one. if a "borrow" occurs (e.g., if the resulting value in register l is 0fh), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: in this example, assume that register pair hl contains 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ldd a,@hl ; a ? (hl) and l ? l?1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0fh the instruction ' jps xxx' is skipped since a "borrow" occurred after the 'ldd a,@hl' and instruction ' jps yyy' is executed.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 71 ldi ? load data memory and increment ldi dst,src operation: operand operation summary bytes cycles a,@hl load indirect data memory to a; increment register l contents and skip on overflow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are incremented by one. if an overflow occurs (e.g., if the resulting value in register l is 0h), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: assume that register pair hl contains the address 2fh and internal ram location 2fh con tains the value 0fh: ld hl,#2fh ldi a,@hl ; a ? (hl) and l ? l+1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0h the instruction ' jps xxx' is skipped since an overflow occurred after the 'ldi a,@hl' and the instruction ' jps yyy' is executed.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 72 nop ? no operation nop operation: operand operation summary bytes cycles ? no operation 1 1 description: no operation is performed by a nop instruction. it is typically used for timing delays. one nop causes a 1-cycle delay: with a 1 s cycle time, five nops would therefore cause a 5 s delay. program execution continues with the instruction immediately following the nop. only the pc is affected. at least three nop instructions should follow a stop or idle instruction. operand binary code operation notation ? 1 0 1 0 0 0 0 0 no operation example: three nop instructions follow the stop instruction to provide a short interval for clock stabilization before power-down mode is initiated: stop nop nop nop
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 73 or ? logical or or dst,src operation: operand operation summary bytes cycles a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 description: the source operand is logically ored with the destination operand. the result is stored in the destination. the contents of the source are unaffected. operand binary code operation notation a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 example: if the accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction or ea, @hl leaves the value 0d7h (11010111b) in the accumulator .
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 74 pop ? pop from stack pop dst operation: operand operation summary bytes cycles rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2 description: the contents of the ram location addressed by the stack pointer is read, and the sp is incremented by two. the value read is then transferred to the variable indicated by the destination operand. operand binary code operation notation rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp+1) sp ? sp+2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp+1), sp ? sp+2 0 1 1 0 0 1 1 0 example: the sp value is equal to 0edh, and ram locations 0efh through 0edh contain the values 2h, 3h, and 4h, respectively. the instruction pop hl leaves the stack pointer set to 0efh and the data pointer pair hl set to 34h.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 75 push ? push onto stack push src operation: operand operation summary bytes cycles rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 description: the sp is then decreased by two and the contents of the source operand are copied into the ram location addressed by the stack pointer, thereby adding a new element to the top of the stack. operand binary code operation notation rr 0 0 1 0 1 r2 r1 1 (sp?1) ? rr h , (sp?2) ? rr l sp ? sp?2 sb 1 1 0 1 1 1 0 1 (sp?1) ? smb, (sp?2) ? srb; (sp) ? sp?2 0 1 1 0 0 1 1 1 example: as an interrupt service routine begins, the stack pointer contains the value 0fah and the data pointer register pair hl contains the value 20h. the instruction push hl leaves the stack pointer set to 0f8h and stores the values 2h and 0h in ram locations 0f9h and 0f8h, respectively.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 76 rcf ? reset carry flag rcf operation: operand operation summary bytes cycles ? reset carry flag to logic zero 1 1 description: the carry flag is cleared to logic zero, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 0 c ? 0 example: assuming the carry flag is set to logic one, the instruction rcf resets (clears) the carry flag to logic zero.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 77 ref ? reference instruction ref dst operation: operand operation summary bytes cycles memc reference code 1 3 * * the ref instruction for a 16k call instruction is 4 cycles. description: the ref instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the ref instruction reference area in program memory. ref reduces the number of program memory accesses for a program. operand binary code operation notation memc t7 t6 t5 t4 t3 t2 t1 t0 pc11?0 = memc7?4, memc3?0 < 1 tjp and tcall are 2-byte pseudo-instructions that are used only to specify the reference area: 1. when the reference area is specified by the tjp instruction, memc.7?6 = 00 pc11?0 ? memc.3?0 + ( memc + 1) 2. when the reference area is specified by the tcall instruction, memc.7?6 = 01 (sp?4) (sp?1) (sp?2) ? pc11?0 sp?3 ? emb, erb, 0, 0 pc11?0 ? memc.3?0 + ( memc + 1) sp ? sp?4 when the reference area is specified by any other instruction, the ' memc' and ' memc + 1' instructions are executed. instructions referenced by ref occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020h to 007fh in rom. in addition, the destination address of the tjp and tcall instructions must be located with the 0fffh address. tjp and tcall are reference instructions for jp/jps and call/calls. if the instruction following a ref is subject to the 'redundancy effect', the redundant instruction is skipped. if, however, the ref follows a redundant instruction, it is executed. on the other hand, the binary code of a ref instruction is 1 byte. the upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction ( x 1/2) becomes the lower address, producing a total of 8 bits or 1 byte (see example 3 below).
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 78 ref ? reference instruction ref (continued) examples: 1. instructions can be executed efficiently using ref, as shown in the following example: org 0020h aaa ld hl,#00h bbb ld ea,#ffh ccc tcall sub1 ddd tjp sub2 ? ? ? org 0080h ref aaa ; ld hl,#00h ref bbb ; ld ea,#ffh ref ccc ; call sub1 ref ddd ; jp sub2 2. the following example shows how the ref instruction is executed in relation to ld instructions that have a 'redundancy effect': org 0020h aaa ld ea,#40h ? ? ? org 0100h ld ea,#30h ref aaa ; not skipped ? ? ref aaa ld ea,#50h ; skipped srb 2
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 79 ref ? reference instruction ref (concluded) examples: 3. in this example the binary code of 'ref a1' at locations 20h?21h is 20h, for 'ref a2' at locations 22h?23h, it is 21h, and for 'ref a3' at 24h?25h, the binary code is 22h : opcode symbol instruction org 0020h 83 00 a1 ld hl,#00h 83 03 a2 ld hl,#03h 83 05 a3 ld hl,#05h 83 10 a4 ld hl,#10h 83 26 a5 ld hl,#26h 83 08 a6 ld hl,#08h 83 0f a7 ld hl,#0fh 83 f0 a8 ld hl,#0f0h 83 67 a9 ld hl,#067h 41 0b a10 tcall sub1 01 0d a11 tjp sub2 ? ? ? org 0100h 20 ref a1 ; ld hl,#00h 21 ref a2 ; ld hl,#03h 22 ref a3 ; ld hl,#05h 23 ref a4 ; ld hl,#10h 24 ref a5 ; ld hl,#26h 25 ref a6 ; ld hl,#08h 26 ref a7 ; ld hl,#0fh 27 ref a8 ; ld hl,#0f0h 30 ref a9 ; ld hl,#067h 31 ref a10 ; call sub1 32 ref a11 ; jp sub2
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 80 ret ? return from subroutine ret operation: operand operation summary bytes cycles ? return from subroutine 1 3 description: ret pops the pc values successively from the stack, incrementing the stack pointer by six. program execution continues from the resulting address, generally the instruction immediately following a call or calls. operand binary code operation notation ? 1 1 0 0 0 1 0 1 pc11?8 ? (sp+1) (sp) pc7?0 ? (sp+2) (sp+3) psw ? emb,erb sp ? sp+ 6 example: the stack pointer contains the value 0fah. ram locations 0fah, 0fbh, 0fch, and 0fdh contain 1h, 0h, 5h, and 2h, respectively. the instruction ret leaves the stack pointer with the new value of 00h and program execution continues from location 0125h. during a return from subroutine, pc values are popped from stack locations as follows: sp ? pc11 ? pc8 sp + 1 0 0 0 0 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 81 rrc ? rotate accumulator right through carry rrc a operation: operand operation summary bytes cycles a rotate right through carry bit 1 1 description: the four bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position. c 3 0 operand binary code operation notation a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) example: the accumulator contains the value 5h (0101b) and the carry flag is cleared to logic zero. the instruction rrc a leaves the accumulator with the value 2h (0010b) and the carry flag set to logic one.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 82 sbc ? subtract with carry sbc dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 description: sbc subtracts the source and carry flag value from the destination operand, leaving the result in the destination. sbc sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. the contents of the source are unaffected. if the carry flag was set before the sbc instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. in this case, the carry bit is subtracted from the destination along with the source operand. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" sbc ea,hl ; ea ? 0c3h ? 0aah ? 1h, c ? "0" jps xxx ; jump to xxx; no skip after sbc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" sbc ea,hl ; ea ? 0c3h ? 0aah ? 0h = 19h, c ? "0" jps xxx ; jump to xxx; no skip after sbc
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 83 sbc ? subtract with carry sbc (continued) examples: 3. if sbc a,@hl is followed by an ads a,#im, the sbc skips on 'no borrow' to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'sbc a,@hl' instruction does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 ? 6 decimal addition (the contents of the address specified by the hl register is 6h): rcf ; c ? "0" ld a,#8h ; a ? 8h sbc a,@hl ; a ? 8h ? 6h ? c(0) = 2h, c ? "0" ads a,#0ah ; skip this instruction because no borrow af ter sbc result jps xxx b. 3 ? 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h sbc a,@hl ; a ? 3h ? 4h ? c(0) = 0fh, c ? "1" ads a,#0ah ; no skip. a ? 0fh + 0ah = 9h ; (the skip function of 'ads a,#im' is inhibited after a ; 'sbc a,@hl' instruction even if an overflow occurs.) jps xxx
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 84 sbs ? subtract sbs dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s description: the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. a skip is executed if a borrow occurs. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 examples: 1. the accumulator contains the value 0c3h, register pair hl contains the value 0c7h, and the carry flag is cleared to logic zero: rcf ; c ? "0" sbs ea,hl ; ea ? 0c3h ? 0c7h, c ? "0" ; sbs instruction skips on borrow, ; but carry flag value is not affected jps xxx ; skip because a borrow occurred jps yyy ; jump to yyy is executed 2. the accumulator contains the value 0afh, register pair hl contains the value 0aah, and the carry flag is set to logic one: scf ; c ? "1" sbs ea,hl ; ea ? 0afh ? 0aah, c ? "1" jps xxx ; jump to xxx ; jps was not skipped since no "borrow" occurred after sbs
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 85 scf ? set carry flag scf operation: operand operation summary bytes cycles ? set carry flag to logic one 1 1 description: the scf instruction sets the carry flag to logic one, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 1 c ? 1 example: if the carry flag is cleared to logic zero, the instruction scf sets the carry flag to logic one.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 86 smb ? select memory bank smb n operation: operand operation summary bytes cycles n select memory bank 2 2 description: the smb instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. the constants 0, 1, and 15 are usually used as the smb operand to select the corresponding memory bank. all references to data memory addresses fall within the following address ranges: please note that since data memory spaces differ for various devices in the sam47 product family, the 'n' value of the smb instruction will also vary. addresses register areas bank smb 000h?01fh working registers 0 0 020h?0ffh stack and general-purpose registers 1e0h?1ffh display registers 1 1 f80h?fffh i/o-mapped hardware registers 15 15 the enable memory bank (emb) flag must always be set to "1" in order for the smb instruction to execute successfully for memory banks 0, 1, and 15. format binary code operation notation n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 example: if the emb flag is set, the instruction smb 0 selects the data memory address range for bank 0 (000h?0ffh) as the working memory bank.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 87 srb ? select register bank srb n operation: operand operation summary bytes cycles n select register bank 2 2 description: the srb instruction selects one of four register banks in the working register memory area. the constant value used with srb is 0, 1, 2, or 3. the following table shows the effect of srb settings: erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' = not applicable. the enable register bank flag (erb) must always be set for the srb instruction to execute successfully for register banks 0, 1, 2, and 3. in addition, if the erb value is logic zero, register bank 0 is always selected, regardless of the srb value. operand binary code operation notation n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 example: if the erb flag is set, the instruction srb 3 selects register bank 3 (018h?01fh) as the working memory register bank.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 88 sret ? return from subroutine and skip sret operation: operand operation summary bytes cycles ? return from subroutine and skip 1 3 + s description: sret is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a call or calls instruction. sret skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. operand binary code operation notation ? 1 1 1 0 0 1 0 1 pc11?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 then skip example: if the stack pointer contains the value 0fah and ram locations 0fah, 0fbh, 0fch, and 0fdh contain the values 1h, 0h, 5h, and 2h, respectively, the instruction sret leaves the stack pointer with the value 00h and the program returns to continue execution at location 0125h. then skips unconditionally. during a return from subroutine, data is popped from the stack to the pc as follows: sp ? pc11 ? pc8 sp + 1 0 0 0 0 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 89 stop ? stop operation stop operation: operand operation summary bytes cycles ? engage cpu stop mode 2 2 description: the stop instruction stops the system clock by setting bit 3 of the power control register (pcon) to logic one. when stop executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. i n application programs, a stop instruction must be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three nop instructions are not used after stop instruction, leakage current could be flown because of the floating state in the internal bus. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 example: given that bit 3 of the pcon register is cleared to logic zero, and all systems are operational, the instruction sequence stop nop nop nop sets bit 3 of the pcon register to logic one, stopping all controller operations (with the exception of some peripheral hardware). the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 90 vent ? load emb, erb, and vector address ventn dst operation: operand operation summary bytes cycles emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location. 2 2 description: the vent instruction loads the contents of the enable memory bank flag (emb) and enable register bank flag (erb) into the respective vector addresses. it then points the interrupt service routine to the corresponding branching locations. the program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. the emb and erb flags should be modified using vent before the vector interrupts are acknowledged. then, when an interrupt is generated, the emb and erb values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. after the return from interrupt (iret) you do not need to set the emb and erb values again. instead, use bitr and bits to clear these values in your program routine. the starting addresses for vector interrupts and reset operations are pointed to by the ventn instruction. these addresses must be stored in rom locations 0000h?0fffh. generally, the ventn instructions are coded starting at location 0000h. the format for vent instructions is as follows: ventn d1,d2,addr emb ? d1 ("0" or "1") erb ? d2 ("0" or "1") pc ? addr (address to branch n = device-specific module address code (n = 0?n) operand binary code operation notation emb (0,1) erb (0,1) adr e m b e r b 0 0 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0, pc12 rom (2 x n) 3?0 ? pc11?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 91 vent ? load emb, erb, and vector address ventn (continued) example: the instruction sequence org 0000h vent0 1,0,reset vent1 0,1,intb vent2 0,1,int0 vent3 0,1,int1 org 000ah vent5 0,1,intt0 causes the program sequence to branch to the reset routine labeled 'reset ,' setting emb to "1" and erb to "0" when reset is activated. when a basic timer interrupt is generated, vent1 causes the program to branch to the basic timer's interrupt service routine, intb, and to set the emb value to "0" and the erb value to "1". vent2 then branches to int0, vent3 to int1, and so on, setting the appropriate emb and erb values.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 92 xch ? exchange a or ea with nibble or byte xch dst,src operation: operand operation summary bytes cycles a,da exchange a and data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory contents 2 2 description: the instruction xch loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. operand binary code operation notation a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 example: double register hl contains the address 20h. the accumulator contains the value 3fh (00111111b) and internal ram location 20h the value 75h (01110101b). the instruction xch ea,@hl leaves ram location 20h with the value 3fh (00111111b) and the extended accumulator with the value 75h (01110101b).
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 93 xchd ? exchange and decrement xchd dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; decrement contents of register l and skip on borrow 1 2 + s description: the instruction xchd exchanges the contents of the accumulator with the ram location addressed by register pair hl and then decrements the contents of register l. if the content of register l is 0fh, the next instruction is skipped. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: register pair hl contains the address 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ld a,#0h xchd a,@hl ; a ? 0fh and l ? l ? 1, (hl) ? "0" jps xxx ; skipped since a borrow occurred jps yyy ; h ? 2h, l ? 0fh yyy xchd a,@hl ; (2fh) ? 0fh, a ? (2fh), l ? l ? 1 = 0eh ? ? ? the ' jps yyy' instruction is executed since a skip occurs after the xchd instruction.
sam47 instruction set s3c72n2/c72n4/p72 n4 5- 94 xchi ? exchange and increment xchi dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; increment contents of register l and skip on overflow 1 2 + s description: the instruction xchi exchanges the contents of the accumulator with the ram location addressed by register pair hl and then increments the contents of register l. if the content of register l is 0h, a skip is executed. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: register pair hl contains the address 2fh and internal ram location 2fh contains 0fh: ld hl,#2fh ld a,#0h xchi a,@hl ; a ? 0fh and l ? l + 1 = 0, (hl) ? "0" jps xxx ; skipped since an overflow occurred jps yyy ; h ? 2h, l ? 0h yyy xchi a,@hl ; (20h) ? 0fh, a ? (20h), l ? l + 1 = 1h ? ? ? the ' jps yyy' instruction is executed since a skip occurs after the xchi instruction.
s3c72n2/c72n4/p72n4 sam47 instruction set 5- 95 xor ? logical exclusive or xor dst,src operation: operand operation summary bytes cycles a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 description: xor performs a bit wise logical xor operation between the source and destination variables and stores the result in the destination. the source contents are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 example: if the extended accumulator contains 0c3h (11000011b) and register pair hl contains 55h (01010101b), the instruction xor ea,hl leaves the value 96h (10010110b) in the extended accumulator.

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